The invention lies in the electronics field. More specifically, the invention relates to a synchronous feedback digital circuit having a minimized switching power loss.
Synchronous digital circuits are clocked circuits which have either a non-cyclic signal flow graph or a cyclic signal flow graph. In synchronous digital circuits, so called glitches, i.e. processes of switching back and forth when data streams are applied to data inputs, can occur when data streams are applied to data inputs of the digital synchronous circuit. The processes of switching back and forth occur until a stable state is reached at the output of the digital circuit.
In digital synchronous circuits which have a non-cyclic signal flow graph, one possibility for reducing the propagation of glitches on the signal paths within the digital circuit is so-called pipelining, i.e. the insertion of clocked registers or buffer stores into the signal paths. The clocked inserted registers act like barriers which block or prevent further propagation of glitches from one logic circuit within the digital circuit to the logic circuit connected downstream.
Propagation of the glitches within the digital circuit can also be achieved by the insertion of logic gates, for example of AND gates, into the non-cyclic signal flow chart.
In synchronous digital circuits having a cyclic signal flow graph, i.e. with feedback signal paths, the customary insertion of registers or buffer stores into the signal propagation path leads to corruption at the output of the digital circuit, i.e., with a constant data stream pattern at the input of the digital circuit, the data stream that is output at the output of the digital circuit is changed undesirably by the insertion of the registers.
The glitches or switching back and forth lead to charge reversal processes between logic circuits within the digital circuit, a switching power loss being produced. This increased switching power loss results in an increased current consumption of the digital circuit and in additional heating. Particularly when the digital circuit is fitted in mobile devices such as mobile telephones, the increased current consumption for the digital circuit can result in the accumulator discharging more rapidly. As a result of the additional heating of the digital circuit on account of the increased switching power loss which is caused by the glitches, additional cooling devices are necessary in densely packed, highly complex integrated circuits.
The object of the invention is to provide a synchronous feedback digital circuit which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which has a minimized switching power loss.
With the above and other objects in view there is provided, in accordance with the invention, a synchronous feedback digital circuit with a minimized switching power loss, comprising:
a data input for receiving an input data stream;
a plurality of logic circuits connected to the data input;
a plurality of clocked registers;
a clock generator for generating an operating clock signal at an operating clock period;
a signal generating device connected to the clock generator and to the clocked registers for generating phase-shifted clock signals for the clocked registers, the phase-shifted clock signals having a phase shift xcfx86i for a specific the register       ϕ          N      -      i      -      1        =                    N        -                  [                      i            ⁢                          xe2x80x83                        ⁢            mod            ⁢                          xe2x80x83                        ⁢            N                    ]                -        1            N        ·    T  
where T is an operating clock period of the operating clock signal, N is a factor, i is a number of registers between the register clocked by the phase-shifted clock signal and the data input of the digital circuit.
In accordance with an added feature of the invention, the registers are flip-flop circuits. Alternatively, the may be latch circuits.
In accordance with an additional feature of the invention, the signal generating device is a phase shift device comprised of a plurality of flip-flop circuits.
In accordance with a concomitant feature of the invention, the digital circuit is produced in CMOS technology.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a synchronous feedback digital circuit having a minimized switching power loss, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.